Research Interests

Acceleration of Sparse Matrix Computation on Many-core Processors

• Sparse Matrix Vector Multiplication (SpMV)
• Sparse General Matrix-Matrix Multiplication (SpGEMM)
• Sparse-Dense Matrix Multiplication (SpMM)

Random Number Generator

• Multiple Recursive Generator with 8th-order Full Primitive Polynomials (MRG8) for Many-core Processors

Machine Learning

• Scikit-learn

Molecular Dynamics Simulation

• All-atom simulation
• Coarse-grained simulation
• Neural network potential

Publication

Lists

• Google Scholar
• Tokyo Tech Research Repository (T2R2)

Journal Papers

• Yusuke Nagasaka, Satoshi Matsuoka, Ariful Azad and Aydın Buluç, “Performance optimization, modeling and analysis of sparse matrix-matrix products on multi-core and many-core processors”, The Journal of Parallel Computing (PARCO), 2019. [DOI]
• Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi “A traffic-aware memory-cube network using bypassing”, Microprocessors and Microsystems, 2022. [DOI]
• Ryo Kanada, Atsushi Tokuhisa, Yusuke Nagasaka, Shingo Okuno, Koichiro Amemiya, Shuntaro Chiba, Gert-Jan Bekker, Narutoshi Kamiya, Koichiro Kato, Yasushi Okuno “Enhanced Coarse-Grained Molecular Dynamics Simulation with a Smoothed Hybrid Potential Using a Neural Network Model”, Journal of Chemical Theory and Computation, ACS Publications, 2023. [DOI]

Conference Papers

• Yusuke Nagasaka, Akira Nukada and Satoshi Matsuoka, “Cache-aware sparse matrix formats for Kepler GPU”, 20th IEEE International Conference on Parallel and Distributed Systems (ICPADS), Hsinchu, Taiwan, December 2014. [DOI] [Slides]
• Yusuke Nagasaka, Akira Nukada and Satoshi Matsuoka, “Adaptive Multi-level Blocking Optimization for Sparse Matrix Vector Multiplication on GPU”, International Conference on Computational Science 2016 (ICCS 2016), San Diego, California, USA, June 2016. [DOI] [Slides]
• Yusuke Nagasaka, Akira Nukada and Satoshi Matsuoka, “High-performance and Memory-saving Sparse General Matrix-Matrix Multiplication for NVIDIA Pascal GPU”, International Conference on Parallel Processing 2017 (ICPP 2017), Bristol, UK, August 2017. [DOI] [Slides]
• Yusuke Nagasaka, Akira Nukada, Satoshi Matsuoka, Kenichi Miura, John Shalf, “MRG8 - Random Number Generation for the Exascale Era”, The Platform for Advanced Scientific Computing Conference (PASC18), Basel, Switzerland, 2018. [DOI] [Slides]
• Yusuke Nagasaka, Satoshi Matsuoka, Ariful Azad and Aydın Buluç, “High-performance sparse matrix-matrix products on Intel KNL and multicore architectures”, International Workshop on Parallel Programming Models and Systems Software for High-End Computing (P2S2), held in conjunction with ICPP 2018, Eugene, Oregon, USA, 2018. [DOI] [arXiv] [Slides]
• Yusuke Nagasaka, Akira Nukada, Ryosuke Kojima, Satoshi Matsuoka, “Batched Sparse Matrix Multiplication for Accelerating Graph Convolutional Networks”, The 19th Annual IEEE/ACM International Symposium in Cluster, Cloud, and Grid Computing (CCGrid 2019), Larnaca, Cyprus, 2019. [DOI] [arXiv] [Slides]
• Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi “Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths”, 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), 2021. [DOI]
• Yusuke Nagasaka, Naoto Fukumoto, “Efficient Collision-Free MTTKRP Algorithm for Multi-core CPUs with Less Memory Usage “, 22nd IEEE International Symposium on Cluster, Cloud and Internet Computing (CCGrid), 2022. [DOI]
• 長坂侑亮, 額田彰, 松岡聡, “GPUのキャッシュを考慮した疎行列ベクトル積計算手法の性能評価”, 情報処理学会研究報告 HPC-144, 横浜, 2014年5月. [DOI]
• 長坂侑亮, 額田彰, 松岡聡, “疎行列ベクトル積計算を対象としたGPU向けメモリアクセス削減手法”, 情報処理学会研究報告 HPC-151, 那覇, 2015年9月. [DOI]
• 長坂侑亮, 額田彰, 松岡聡, “メモリ使用量を抑えた疎行列疎行列積計算のGPU高速化”, 情報処理学会研究報告 HPC-156, 小樽, 2016年9月. [DOI]
• 長坂侑亮, 額田彰, 小島諒介, 松岡聡, “GraphCNN向けの疎行列積計算Batch最適化”, 情報処理学会研究報告 HPC-167, 那覇, 2018年12月. [DOI]
• 長坂侑亮, 額田彰, 小島諒介, 松岡聡, “小疎行列積計算のGPU最適化”, 情報処理学会研究報告 HPC-168, 加賀, 2019年3月. [DOI]
• 長坂侑亮, 福本尚人, ” 疎なテンソルに対するMTTKRP計算のCPU向け高速化”, 情報処理学会研究報告 HPC-185, 下関, 2022年7月. [DOI]

Posters

• Yusuke Nagasaka, Akira Nukada and Satoshi Matsuoka, “Cache-aware Sparse Matrix Format for GPU”, International Superconputing Conference (ISC’14) HPC in Asia Posters, Leipzig, Germany, June 2014.
• Yusuke Nagasaka, Akira Nukada and Satoshi Matsuoka, “Multi-Level Blocking Optimization for Fast Sparse Matrix Vector Multiplication on GPUs”, The International Conference for High Performance Computing, Networking, Storage and Analysis (SC15) Technical Program Posters, Austin, Texas, USA, November 2015. [Link]
• Yusuke Nagasaka, “Fast Sparse Matrix Vector Multiplication with Highly-Compressed Sparse Format”, GPU Technology Conference (GTC2016), San Jose, CA, USA, April 2016. [Link]
• Yusuke Nagasaka, Akira Nukada and Satoshi Matsuoka, “Fast Sparse General Matrix-Matrix Multiplication on GPU with Low Memory Usage”, The International Conference for High Performance Computing, Networking, Storage and Analysis (SC16) Technical Program Posters, Salt Lake City, Utah, USA, November 2016. [Link]
• Yusuke Nagasaka, “Fast and Memory-saving SpGEMM Algorithm for New Pascal Generation GPU”, GPU Technology Conference (GTC2017), San Jose, CA, USA, May 2017. [Link]
• Yusuke Nagasaka, “Boosting GCN Application with Batched Sparse Matrix Multiplication”, GPU Technology Conference (GTC2019), San Jose, CA, USA, March 2019. [Link]
• 長坂侑亮, “GPUでのキャッシュ再利用性を考慮した列分割型疎行列フォーマットの性能評価”, GPU テクノロジ・カンファレンス(GTC Japan 2014), 東京, 2014年7月.
• 長坂侑亮, “多段階ブロッキングによるメモリアクセス量削減を図ったGPU向け疎行列ベクトル積計算手法の性能評価”, GPU テクノロジ・カンファレンス(GTC Japan 2015), 東京, 2015年9月.
• Yusuke Nagasaka, “MRG8 - High Throughput Random Number Generation for GPU”, GPU テクノロジ・カンファレンス(GTC Japan 2018), 東京, 2018年9月.

Talks

• Yusuke Nagasaka “Exploiting GPU Caches in Sparse Matrix Vector Multiplication”, GPU Technology Conference (GTC2015), San Jose, CA, USA, March 2015. [Link]
• Yusuke Nagasaka, Akira Nukada and Satoshi Matsuoka, Ariful Azad and Aydın Buluç, “Efficient Sparse General Matrix-Matrix Multiplication Algorithms for Many-Core Processors”, SIAM PP 2018, Tokyo, Japan, March 2018. [Link]

Awards

• 2015年度情報処理学会コンピュータサイエンス領域奨励賞. [Link]
• 2019年度情報処理学会山下記念研究賞. [Link]

Software

nsparse

Fast Sparse Matrix Library for GPU. Supporting SpMV with AMB format and Hash-table based SpGEMM.
GitHub Link

mtspgemm

Fast SpGEMM kernel for Multi-thread CPUs (mainly for Intel KNL) Bitbucket Link

Batched SpMM

Batched sparse-dense matrix multiplication kernel between small matrices for GPU GitHub Link

Experiences

Joint Research

2015, 2016

学際大規模情報基盤共同利用・共同研究拠点 共同研究
jh150046-NA24 “超大規模シミュレーションのためのアーキテクチャ特性を考慮した通信削減技術”

Teaching Assistant

2016, 2017

Working as teaching assistant of the courses on computer system and high-performance computing at Tokyo Institute of Technology.

Internship

May - July, 2017

Summer internship at Lawrence Berkeley National Laboratory (LBNL).

Education

Bachelor of Science

Tokyo Institute of Technology, Dept. of Information Science
April 2010 - March 2014

Bachelor Thesis: “キャッシュを考慮したSPMVのGPU高速化”
Supervisor: Prof. Satoshi Matsuoka

Master of Science

Tokyo Institute of Technology, Dept. of Mathematical and Computing Sciences
April 2014 - March 2016

Master Thesis: “メモリアクセス量削減による疎行列ベクトル積計算のメニーコア向け高速化”
Supervisor: Prof. Satoshi Matsuoka

Doctor of Science

Tokyo Institute of Technology, Dept. of Mathematical and Computing Science
April 2016 - March 2019

Doctor Thesis: “Performance Optimization of Sparse Matrix Kernels for Many-core Architectures (メニーコアアーキテクチャにおける疎行列計算の性能最適化)” Supervisor: Prof. Satoshi Matsuoka

Contact

E-mail: nagasaka.mlab [at] gmail.com